1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device to form transistors for a system on a chip.
2. Discussion of Related Art
Systems are commonly made on chips to obtain improved integration of semiconductor devices. In such systems formed on chips, different kinds of voltages are often required. For example, logic devices needing low voltages and other devices (such as erasable programmable read only memories (EPROMs) or electrically erasable programmable read only memories (EEPROMs)) needing high voltages are formed on the same chip. That is, the logic devices are embedded, short-channel, and low-voltage devices whereas the high-voltage devices such as EPROMs or EEPROMs employ high voltages of about 10V.
FIGS. 1A to 1G depict a method of manufacturing a conventional semiconductor device.
As shown in FIG. 1A, a region Y of a cell region, a region X of the cell region, a peripheral region, a high-voltage applied region, and a separation region are defined on a p-type semiconductor substrate 11. The cell region and the high-voltage applied region correspond to high-voltage devices, and the peripheral region corresponds to a logic device An n-well A is formed in a portion of substrate 11 where a p-channel metal oxide semiconductor (PMOS) device will be formed, and an oxidation process is carried out on a separation region of substrate 11 to form a plurality of field oxide films 12. A first photoresist film 13 is then applied over all the substrate 11. The first photoresist film 13 is selectively exposed to light, developed and removed from the portion corresponding to the cell region. Ions 14, for controlling a first threshold voltage V.sub.th, are implanted to the cell region of substrate 11 using the selectively etched photoresist film 13 as a mask.
As shown in FIG. 1B, the remainder of the first photoresist film 13 is removed, and a tunneling oxide film 15 is formed to a thickness of 100 .ANG. on substrate 11 by a thermal oxidation process performed on the surface of substrate 11. As shown in FIG. 1C, a first polycrystalline silicon film 16 and a second photoresist film 17 are formed on the surface, and the second photoresist film 17 is selectively etched by photolithography to remain on a portion of the cell region where floating gates will be formed. Then, the first polycrystalline silicon film 16 is selectively etched by photolithography using the selectively etched second photoresist film 17 as a mask. Thus, a plurality of floating gates 16 are formed on tunneling oxide film 15 of the cell region.
As shown in FIG. 1D, the remainder of the second photoresist film 17 is removed. Next, an oxide/nitride/oxide (ONO) film 18 and a third photoresist film 19 are formed on floating gates 16. The third photoresist film 19 is selectively etched by photolithography to remain on the cell region only, and the ONO film 18 is selectively etched by photolithography using third photoresist film 19 as a mask. Then, ions to control a second threshold voltage are implanted into the peripheral region and the high-voltage applied region of semiconductor substrate 11
As shown in FIG. 1E, the tunneling oxide film 15 is selectively etched through photolithography using the third photoresist film 19 as a mask, and the third photoresist film 19 is then removed. A first gate oxide film 21 is formed to a thickness of 200 .ANG. or less in the peripheral region and the high-voltage applied region by thermal oxidation of the surface of substrate 11.
Next, a fourth photoresist film is applied over all the surface. The fourth photoresist film is selectively etched from the peripheral region only, and the first gate oxide film 21 is selectively etched using the selectively etched fourth photoresist film as a mask. The fourth photoresist film is then removed. A second gate oxide film 22 is formed to a thickness of 150 .ANG. in the peripheral region using thermal oxidation.
As shown in FIG. 1F, a second polycrystalline silicon film and a fifth photoresist film 26 are formed over all the surface including second gate oxide film 22. Fifth photoresist film 26 is selectively etched to remain on a control gate of the cell region, gates of the peripheral region and gates of the high-voltage applied region. The second polycrystalline silicon is selectively etched by using the selectively etched fifth photoresist film 26 as a mask to form a control gate 23, a plurality of first gates 24, and a plurality of second gates 25 on each floating gate 16 of the cell region, second gate oxide film 22 of the peripheral region, and first gate oxide film 21 of the high-voltage applied region, respectively.
As shown in FIG. 1G, the remainder of the fifth photoresist film 26 is removed, and a sixth photoresist film is formed on the surface, including the plurality of second gates 25. The sixth photoresist film is selectively etched to remain on region Y of the cell region, the peripheral region, and the high-voltage applied region, and gate patterns of region X of the cell region only.
Control gate 23, ONO film 18, and floating gates 16 are selectively etched using the selectively-etched sixth photoresist film as a mask to form the gate patterns, and the remainder of the sixth photoresist film is removed. A seventh photoresist film is deposited over all the surface, and is then selectively etched to remain on n-well A only. N-type ions are implanted by using the selectively etched seventh photoresist film, field oxide films 12, control gate 23, and first and second gates 24 and 25 as a mask, and the seventh photoresist film is then removed.
An eighth photoresist film is deposited over all the surface, and the eighth photoresist film is selectively etched to be removed from the upper part of n-well A. P-type ions are implanted using the selectively etched eighth photoresist film as a mask, and the remainder of the eighth photoresist film is then removed. A drive-in diffusion is performed on the overall surface, and source/drain impurity regions 27 are formed within the portion of semiconductor substrate 11 at both sides of each floating gate 16 of region X of the cell region, the portion of substrate 11 at both sides of first and second gates 24 and 25, and n-well A between second gates 25.
The conventional method of manufacturing a semiconductor device has a number of problems.
For example, in the manufacturing method of a system on a chip as described, the high-voltage device and logic device have the same source/drain regions, and a short-channel device with a high impurity concentration cannot be made in the logic device thereby lowering the performance efficiency of the logic device.
Further, in the formation of a short-channel device in the logic device, a high junction breakdown voltage cannot be obtained in the high-voltage applied region of the high-voltage device due to the semiconductor substrate of high concentration and the shallow source/drain region. Thus, the performance efficiency of the high-voltage device is reduced.
Moreover, since the junction breakdown voltage of the logic device transistor in a device of 0.8 to 1.0 .mu.m is more than 10V, the logic device and the high voltage device share the source/drain regions, and because the logic device transistor of 0.35 to 0.5 .mu.m is less than 10V, the logic device and the high voltage device cannot share the source/drain regions.